1. Field of the Invention
The present invention relates to flipflops and, more particularly, to an edge triggered flipflop that can tolerate arbitrarily slow clock edge rates.
2. Description of the Related Art
A D flipflop is a logic element that has a D input, a clock input and a Q output, where the state of the Q output depends upon the state of the D input when a triggering clock edge is detected. A rising edge triggered D flipflop is a flipflop where the triggering or active clock edge is the rising clock edge. Similarly, a falling edge triggered D flipflop is a flipflop where the triggering or active clock edge is the falling clock edge.
FIG. 1A shows a circuit symbol that illustrates a prior-art, rising edge triggered D flipflop FF1, while FIG. 2A shows a circuit symbol that illustrates a prior-art, falling edge triggered D flipflop FF2. FIGS. 1B-1D show timing diagrams that illustrate the operation of rising edge triggered flipflop FF1, while FIGS. 2B-2D show timing diagrams that illustrate the operation of falling edge triggered flipflop FF2.
As shown in FIGS. 1A and 2A, flipflops FF1 and FF2 both have a D input, a clock input and a Q output. As shown in FIGS. 1B-1D, the logic state on the D input of flipflop FF1, as illustrated by the data signal DATA, is captured on the rising edge of the clock signal CLK. In addition, the state of the Q output, as illustrated by the output signal QOUT, assumes the state of the D input a propagation time after the rising edge of the clock signal.
Similarly, as shown in FIGS. 2B-2D, the logic state on the D input of flipflop FF2, as illustrated by the data signal DATA, is captured on the falling edge of the clock signal CLK. In addition, the state of the Q output, as illustrated by the output signal QOUT, assumes the state of the D input a propagation time after the falling edge of the clock signal. Thus, as shown in FIGS. 1A-1D and 2A-2D, an edge triggered flipflop can be clocked by either a rising clock edge or a falling clock edge.
No matter which clock edge is used to clock an edge triggered flipflop, the clock edge rate is of critical importance. Thus, if the active clock edge is extremely fast (short rise time), most flipflops will be able to correctly respond to it. On the other hand, if the active clock edge is extremely slow (long rise time), most flipflops will not correctly respond to it. In this case, input data on the D input of the flipflop will directly “flow-through” to the Q output of the flipflop.
In other words, when the active clock edge transition occurs very slowly, a logic signal change on the D input pin of the flipflop can directly propagate to the Q output pin of the flipflop. Of course, when this “flow-through” action occurs, it causes the flipflop to behave like a flow-through latch instead of an edge triggered flipflop. In this case, the flipflop has malfunctioned because it is no longer behaving as an edge triggered logic element.
FIG. 3 shows a circuit diagram that illustrates a prior-art, rising edge triggered D flipflop 300. As shown in FIG. 3, flipflop 300 includes an inverter 310, a master latch 312, and a slave latch 314. Inverter 310 generates an inverted clock signal CLKZ, in response to a clock signal CLK.
Master latch 312 has two transmission gates X1 and X2 and two inverters U2 and U3. Transmission gate X1 has an input connected to the D input of flipflop 300, and an output connected to an intermediate node D1. Inverter U2 has an input connected to intermediate node D1, and an output connected to the master latch output node D1Z. Inverter U3 has an input connected to the master latch output node D1Z, and an output connected to the input of transmission gate X2. The output of transmission gate X2 is connected to intermediate node D1.
Similarly, slave latch 314 also has two transmission gates X3 and X4 and two inverters U4 and U5. Transmission gate X3 has an input connected to the master latch output node D1Z, and an output connected to an intermediate node D2Z. Inverter U4 has an input connected to intermediate node D2Z, and an output connected to the Q output of flipflop 300. Inverter U5 has an input connected to the Q output, and an output connected to the input of transmission gate X4. The output of transmission gate X4 is connected to intermediate node D2Z.
In operation, when the clock signal CLK is low and the inverted clock signal CLKZ is high, transmission gate X1 will be on and transmission gate X2 will be off. Since transmission gate X1 is on, the logic state on the D input of flipflop 300 can propagate through transmission gate X1, inverter U2, and through inverter U3.
However, since transmission gate X2 is off, the output of inverter U3 cannot drive intermediate node D1. In other words, the master latch loop is open, and thus changes in the logic state on the D input of flipflop 300 can propagate through master latch 312, up to the output of inverter U3.
When the clock signal CLK is high and the inverted clock signal CLKZ is low, transmission gate X1 will be off and transmission gate X2 will be on. Since transmission gate X2 is on, the logic state on intermediate node D1 can propagate through inverter U2, inverter U3, and transmission gate X2. In other words, the master latch loop is closed, and thus master latch 312 cannot respond to changes in the logic state on the D input of flipflop 300 because transmission gate X1 is off.
With respect to slave latch 314, when the clock signal CLK is high, transmission gate X3 will be on and transmission gate X4 will be off. Since transmission gate X3 is on, the logic state on master latch output node D1Z can propagate through transmission gate X3, inverter U4 and inverter U5. However, since transmission gate X4 is off, the output of inverter U5 cannot drive node D2Z. In other words, the slave latch loop is open, and thus changes in the logic state on master latch output node D1Z can propagate through slave latch 314, up to the output of inverter U5.
When the clock signal CLK is low and the inverted clock signal CLKZ is high, transmission gate X3 will be off and transmission gate X4 will be on. Since transmission gate X4 is on, the logic state on intermediate node D2Z can propagate through inverter U4, inverter U5 and transmission gate X4. In other words, the slave latch loop is closed, and thus slave latch 314 can not respond to changes in the logic state on master latch output node D1Z because transmission gate X3 is off.
In summary, when the clock signal CLK is low, master latch output node D1Z is logically connected to the D input of flipflop 300, but is logically disconnected from the Q output of flipflop 300. Furthermore, when the clock signal CLK is high, master latch output node D1Z is logically connected to the Q output of flipflop 300, but is logically disconnected from the D input of flipflop 300.
Referring to FIG. 3, when the clock signal CLK is rising, the inverted clock signal CLKZ will be falling (and vice versa). Thus, when the clock signal CLK changes its logic state very slowly, the inverted clock signal CLKZ will also change its logic state very slowly. In this case, the CLK and CLKZ signals cannot be considered to be logical complements of each other because they can both be at the same voltage level for a considerable amount of time.
As shown in FIG. 3, if the clock signal CLK and the inverted clock signal CLKZ are both at the same voltage level, the master latch transmission gate X1 and the slave latch transmission gate X3 can both be on at the same time. This condition can cause the D input of flipflop 300 to “flow-through” (i.e., directly propagate) to the Q output of flipflop 300, causing a logic malfunction. Thus, in order to eliminate this malfunction, there is a definite need for a flipflop that can respond to arbitrarily slow clock edge rates without causing flow-through.